Google is reportedly readying its own chip for Pixel and Chromebook devices. A report says that the tech giant has partnered with Samsung to work on custom chips for Pixel devices, and it is codenamed as Whitechapel. Google is expected to use Samsung’s 5-nanometer technology to manufacture this chip. It is likely to be introduced to the world in Pixel phones launched next year, not in 2020. If this new development holds any weight, then it could prove to be a blow to Qualcomm – current supplier to Google for all Pixel phone chips.
According to the report by Axios, which is citing anonymous sources, Google has already received the first working versions of this chip, and looks to integrate it in next year’s Pixel device. The chip is codenamed Whitechapel and it includes an eight-core ARM processor. The chip will include hardware optimised for Google’s machine-learning technology. The report says that the chip will also have dedicated space for improving Google Assistant performance and “always-on” capabilities.
As mentioned, the company has partnered with Samsung that also produces its own Exynos lineup, and has also manufactured Apple’s A-series chips as well. Google reportedly plans to build a version of the chip for Chromebooks as well, after it succeeds with Pixel phones. There’s a lot that goes into making a mobile processor, and Google will have to ensure that it manages to succeed in all aspects to compete with Apple. The Cupertino giant integrates its own A-series Bionic chips inside the iPhone models.
A recent report out of Korea also suggested that Samsung is working with Google to build a custom chipset. This chip is rumoured to feature eight CPU cores with four Cortex-A55, two Cortex-A78 cores, and two Cortex-A76 cores. For this new chip, the report says that Samsung has removed its own image signal processor (ISP) and neural processing unit (NPU), and have integrated Google’s visual core and the search giant’s NPU instead. This chip is also expected to bring ARM’s unannounced Mali MP20 GPU that is based on Borr microarchitecture.